About Anti-Tamper Digital Clocks
About Anti-Tamper Digital Clocks
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implies for assessing that takes advantage of the plurality of delayed monotone signals to detect a voltage fault and
Yet another aspect of the creation may perhaps reside in an apparatus for detecting clock tampering, comprising a circuit that gives a monotone sign, a plurality of resettable hold off line segments, and an Examine circuit. The circuit delivers the monotone signal through a clock Appraise period of time affiliated with a clock. The plurality of resettable delay line segments hold off the monotone signal to produce a respective plurality of delayed monotone alerts.
twenty five. The tactic for detecting voltage tampering as defined in claim 23, wherein utilizing the clock to trigger the Consider circuit comprises utilizing a clock edge at an stop in the Consider time period to induce the evaluate circuit.
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What is claimed is: 1. A technique for detecting clock tampering, comprising: supplying a plurality of resettable hold off line segments, wherein resettable hold off line segments concerning a resettable hold off line section associated with a minimal hold off time plus a resettable delay line phase linked to a optimum hold off time are Just about every connected with discretely raising delay periods;
Resettable hold off line segments concerning a resettable delay line section connected to a bare minimum delay time plus a resettable delay line section associated with a optimum delay time are Every single linked to discretely escalating delay occasions. An Examine circuit is induced by a clock and takes advantage of the plurality of delayed monotone indicators to detect a voltage fault.
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39. The apparatus for detecting voltage tampering as described in assert 37, whereby the Examine circuit is brought on by a clock edge at an stop from the Consider period of time.
a first plurality of resettable delay line segments that every hold off the 1st monotone sign to generate a respective to start with plurality of delayed monotone alerts, whereby resettable hold off line segments involving a resettable hold off line section linked to a least hold off time plus a resettable hold off line segment affiliated here with a optimum hold off time are each related to discretely raising delay periods;
A monotone sign is furnished all through a clock evaluate period of time related to a clock. The monotone sign is delayed using Every single in the plurality of resettable delay line segments to generate a respective plurality of delayed monotone indicators. The clock is accustomed to result in an Consider circuit that utilizes the plurality of delayed monotone signals to detect a clock fault.
forty. The apparatus for detecting voltage tampering as described in declare 37, whereby the Consider circuit establishes whether or not the volume of types within the plurality of delayed monotone indicators differs from the drinking water level selection by greater than a predetermined threshold to detect the voltage fault.
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